1. Field of the Invention
The present invention relates generally to semiconductor devices, and, more particularly to a structure in which surge withstanding amount of an insulated gate field effect transistor with a high breakdown voltage (referred to as MIS FET with a high breakdown voltage hereinafter) can be increased. The present invention further relates to a method of manufacturing an MIS FET with a high breakdown voltage.
2. Description of the Background Art
FIG. 7 is a plan view of a semiconductor device comprising a conventional MIS FET (Metal Insulator Semiconductor Field Effect Transistor) with a high breakdown voltage. FIGS. 8 and 9A show diagrams of sectional structures taken along section lines VIII--VIII and IX--IX in FIG. 7. Referring to these FIGURES, a conventional MIS FET with a high breakdown voltage comprises a gate electrode 2 on a major surface of a p type silicon substrate 13 through a thin gate insulation film 9, and further comprises a pair of n.sup.+ regions; drain region 1 and source region 3 at the opposite sides of the gate electrode 2 on the surface of the p type silicon substrate 13. The n.sup.+ drain region 1 is surrounded by an n.sup.-- drain region 4 of a low concentration. A field oxide film 7 having a larger film thickness than that of the gate insulation film 9 is formed between the n.sup.-- drain region 4 and the gate electrode 2. An n.sup.- source region 6 of the low concentration is formed at an end portion on a channel side of the n.sup.+ source region 3. A double structure of the n.sup.+ source region 3 and the n.sup.- source region 6 constitutes a so-called LDD (Lightly Doped Drain) structure. Gate sidewalls 8 are formed on sidewalls of the gate electrode 2 and the LDD structure in the source region is formed by using the gate side wall 8. An interlayer insulating film 10 is formed on the major surface of the p type silicon substrate 13. An aluminum interconnection layer 5 is connected to the n.sup.+ drain region 1 and the n.sup.+ source region 3 through a contact hole 22 formed in each interlayer insulating film 10. A surface of the interlayer insulating film 10 and the like is covered with a passivation film 11. Each of the MIS FETs formed on the surface of the p type silicon substrate 13 is insulated and isolated through a field isolation oxide film 23. A p.sup.+ channel stopper 12 is formed under the field isolation oxide film 23.
In the above described MIS FET, a part of the gate insulation film is formed of the thick field oxide film 7. Such a structure is directed to the increase of a breakdown voltage between a source and a drain, because the formation of the thick oxide film 7 alleviates an electric field near the drain region. In addition, the n.sup.-- drain region 4 having a lower concentration than that of the n.sup.+ drain region 1 is formed around the n.sup.+ drain region 1. Formation of the n.sup.-- drain region 4 of the low concentration allows a depletion layer to expand toward the drain side, thereby alleviating concentration of the electric field near the drain. This alleviates the electric field between the source and the drain to increase a breakdown voltage between the source and the drain.
Steps of manufacturing the above described MIS FET with the high breakdown voltage will be described in the following. FIGS. 11A to 11I are sectional views of the structure of the MIS FET with the high breakdown voltage shown in FIG. 8 in the steps of manufacturing the same and FIGS. 12A to 12H are sectional views of the structure shown in FIG. 9 in the manufacturing steps thereof.
First, referring to FIGS. 11A and 12A, an underlying oxide film 14 and a nitride film 15 are sequentially formed on the surface of the p type silicon substrate 13.
Then, a resist pattern 16 of a predetermined configuration is formed on the surface of the nitride film 15.
Referring to FIGS. 11B and 12B, the nitride film 15 is selectively removed into a predetermined configuration using the resist pattern 16 as a mask. Furthermore, a resist is again applied on the surface of the p type silicon substrate 13 and which is patterned into a predetermined configuration to form a resist pattern 17. Then, boron ion 24 is implanted into the surface of the p type silicon substrate 13 using the resist pattern 17 as a mask, thereby forming a p.sup.+ channel stopper 12.
Referring to FIGS. 11C and 12C, after the removal of the resist patterns 16 and 17, a resist is again applied to the surface of the p type silicon substrate 13 to form an additional resist pattern 18 by using photolithography. Then, phosphorus ion or arsenic ion 25 is implanted into the surface of the p type silicon substrate 13 using the resist pattern 18 and the nitride film 15 as masks. This ion implantation forms the n.sup.-- drain region 4 of the low concentration at a predetermined position of the surface of the p type silicon substrate 13.
Referring to FIGS. 11D and 12D, after the removal of the resist pattern 18 and the nitride film 15, a field oxide film 7 and a field isolation oxide film 23 are formed on a region of the surface of the p type silicon substrate 13 which is not covered with the nitride film 15 by using a thermal oxidation process. Thereafter, the nitride film 15 is removed. Through this process, the n.sup.-- drain region 4 is formed under the field oxide film 7 and the p.sup.+ channel stopper 12 is formed under the field isolation oxide film 23.
Referring to FIGS. 11E and 12E, the underlying oxide film 14 on the surface of the p type silicon substrate 13 is removed. Then, a gate insulation film 9 is formed on the surface of the p type silicon substrate 13 from which the underlying oxide film 14 is removed, by the thermal oxidation process. Furthermore, a polycrystalline silicon layer 2 is formed on the gate oxide film 9 by using CVD (Chemical Vapor Deposition). Then, a resist is applied on the major surface of the polycrystalline silicon layer 2 to form a resist pattern 19 of a predetermined configuration.
Referring to FIGS. 11F and 12F, the polycrystalline silicon layer 2 is selectively etched to be removed using the resist pattern 19 as a mask. Through this process, the gate electrode 2 is formed. Then, after the removal of the resist pattern 19, phosphorus ion 26 is implanted into the p type silicon substrate 13 using the gate electrode 2 as a mask. This ion implantation forms an n.sup.- source region 6 in a predetermined region of the surface of the p type silicon substrate 13 which will be a source region, and an n type impurity region of a low concentration is formed in a region which will be a drain region.
Referring to FIG. 11G, after the formation of the CVD oxide film on the surface of the silicon substrate 13, the CVD oxide film is anisotropically etched, thereby forming a gate sidewall 8 on a sidewall of the gate electrode 2. Furthermore, arsenic ion 27 is implanted into the surface of the p type silicon substrate 13 using the gate electrode 2 and the gate sidewall 8 as masks. This ion implantation forms an n.sup.+ drain region and an n.sup.+ source region 3.
Referring to FIGS. 11H and 12G, after the thermal process of the entire silicon substrate, an interlayer insulating film 10 is deposited on the surface of the silicon substrate using the CVD method. Then, the resist is applied on the surface, thereafter which is patterned into a predetermined configuration to form a resist pattern 20. Then, using the resist pattern 20 as a mask the interlayer insulating film 10 is selectively etched, thereby forming a contact hole 22.
Referring to FIGS. 11I and 12H, an aluminum-silicon layer 5 is formed on the surface of the interlayer insulating film 10 by a sputtering method. Furthermore, a resist pattern 21 of a predetermined configuration is formed on the surface of the aluminum-silicon layer 5.
Thereafter, the aluminum-silicon layer 5 is etched into a predetermined configuration to form an aluminum interconnection layer 5. Then, the whole surface is covered with a passivation film 11. The above described processes complete a manufacturing of the MIS FET with the high breakdown voltage.
One of the causes of a malfunction of a semiconductor device is surge breakdown phenomenon in which a high surge voltage caused by static electricity charged on an IC package incorporated in the above described MIS FET with the high breakdown voltage permanently breaks down a junction region of a transistor and the like. Accordingly, the above described MIS FET with the high breakdown voltage is required to have a predetermined withstanding amount (referred to as surge withstanding amount hereinafter) against the surge breakdown. An evaluation test of the surge withstanding amount of the conventional MIS FET with the high breakdown voltage is performed using a surge withstanding amount measuring device shown in FIG. 13. The shown surge withstanding amount measuring device is for testing a breakdown state of a sample transistor by storing a predetermined amount of electric charges from a direct current power supply in a condenser C, and thereafter switching a circuit and discharges the electric charges stored between a source and a drain of a sample MIS FET. As a result of the evaluation test of the device, the surge withstanding amount of the above described MIS FET with the high breakdown voltage is approximately 200 V in both of a positive bias and a negative bias, which is far lower than a target value of 300 V.
Model examples of the surge breakdown are as follows.
(1) Due to an inherentrly slow response of a transistor of this type to a surge voltage, a voltage applied to the circuit is instantaneously raised above a breakdown voltage, resulting in breakdown.
(2) Currents and electric fields are concentrated due to the surge voltage to break down a pn junction.
Regarding such models of the surge breakdown, the present invention is particularly directed to the resolution of the item (2). FIG. 9B is a partially enlarged view of FIG. 9A. FIG. 10 is an enlarged plan view of FIG. 7. Namely, referring to FIGS. 9A, 9B and 10, assuming that a surge voltage, a high voltage is applied to a drain of an MIS FET with the high breakdown voltage. In this case, a surge current flows from the drain region 1 to the silicon substrate 13 due to avalanche breakdown phenomenon. Then, this flow of the surge current prevents a pn junction between the drain region 1 and the silicon substrate 13 from being broken down. However, the N.sup.+ drain region 1 is surrounded by the n.sup.-- drain region 4. The n.sup.-- drain region 4 alleviates concentration of the electric field near the n.sup.+ drain region 1. FIG. 9B shows distribution of the electric field near the n.sup.+ drain region 1. The formation of the n.sup.-- drain region 4 causes the spacing between the electric field distribution curves 35 to be large and the gradient thereof to be gentle near the n.sup.+ drain region 1. As a result, the avalanche breakdown is less likely to occur, so that the surge current 32 is less likely to be flowed from the n.sup.+ drain region 1 to the substrate 13. In such a state, the electric field is concentrated at the part which is structurally discontinuous indicated by the arrow A in the drawing.
As the foregoing, in the conventional MIS FET with the high breakdown voltage, the existence of the n.sup.-- drain region 4 capable of improving the drain breakdown voltage prevents the increase of the surge withstanding amount.
Therefore, there is a need to provide an arrangement for more effectively dissipating a surge voltage consistent with retaining of high voltage breakdown properties of an MIS FET provided by the n.sup.-- region which prevents the increase of surge withstanding amount.